1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory, and more particularly, to a control circuit for use in, for example, a NAND type flash memory to control writing of the number of rewrites of data.
2. Description of the Related Art
FIG. 2 is an equivalent circuit diagram showing an example of a NAND cell taken out from a portion of a certain cell block BLOCKm as NAND cells used in cell block of a NAND type flash memory.
The NAND cell is composed of 16 memory cells CT0 to CT15 connected in series. One ends of the memory cells are connected to bit lines BLi (BLn, BLn+1, . . . ) through a drain side selection gate transistor DGT, while the other ends thereof are connected to a source line through a source side selection gate transistor SGT. Each of the memory cells CT0 to CT10 is composed of a cell transistor having a double layer gate structure of a floating gate and a control gate, and word lines WLi (WL0 to WL15) are connected to the control gate.
Further, a drain side selection gate line SGD is connected to the control gate of the drain side selection gate transistor DGT, while a source side selection gate line SGS is connected to the control gate of the source side selection gate transistor SGT.
An example of an operation of the NAND type flash memory and an example of an operation of the NAND cell will be briefly described.
Write (program) and erase to the NAND cell are executed by supplying an FN tunnel current to a tunnel oxide film of the cell transistor and injecting and discharging electrons into and from the floating gate of the cell transistor.
That is, in write, the potential of the bit lines BLi is set to the ground potential (Gnd, 0V) and a write voltage Vpgm (for example, 20V) is applied to a selected word line, thereby electrons are injected into the floating gate by a large potential difference caused by the floating gate and a channel of a selected cell transistor. At this time, a power-supply voltage Vdd is supplied to the drain side selection gate line SGD connected in series to the selected cell transistor, and the drain side selection gate transistor DGT is conducting. Further, a non-selection word line write voltage Vpass (for example, 10V) is applied to non-selected word lines and the non-selected cell transistors are conducting, thereby the potential of the bit lines BLi is transferred to the channel portion of the selected cell transistor. A 0 volt is supplied to the source side selection gate line SGS, and the source side selection gate transistor SGT is nonconducting.
Since write is executed at a time to a one page including a plurality of cell transistors commonly connected as a unit to a single word line, there are cell transistors whose data is set to “1” (which have no electrons injected into the floating gates thereof and keep an erased state) in the plurality of cell transistors to which write is executed at the same time.
At the beginning of write to the selected cell transistor having the data 1, when the potential of the word line reaches Vpgm or Vpass after a bit line potential Vdd is transferred to the channel of the cell transistor, the potential of the channel portion is risen by a gate capacitance. At this time, when the potential of the channel of the selection cell transistor becomes higher than Vdd+Vth, the drain side selection gate transistor DGT, which is connected in series to the selected cell transistor, become nonconducting because Vdd is applied to the gate line SGD.
The potential of the channel of the selected cell transistor rises to about 9V while this is determined depending on a ratio of the capacitance between the word line and the floating gate and the capacitance between the floating gate and the channel. With the above operation, since the potential difference between the floating gate and the channel of the selected cell transistor lowers, the FN tunnel current decreases in proportion to the square of an electric field, thereby no writing is executed to the selected cell transistor in an ordinary write time and the cell transistor keeps an erased state.
To execute write to the one page at a time, data registers/sense amplifiers are connected in correspondence to the respective bit lines and temporarily hold write data, respectively.
FIG. 8 is a circuit diagram showing an example of a sense amplifier/data register taken out from the data registers also acting as the sense amplifiers used in the NAND type flash memory in detail.
The sense amplifier/data register is arranged such that a pair of sense input transistors SA0 and SA1, and a pair of I/O gate transistors CTS, which are driven by a column selection signal CSL, are connected to a data register (latch circuit) REG composed of two cross-connected inverters. The source common connection node of the pair of sense input transistors SA0 and SA1 is connected the ground potential Gnd through a sense amplifying NMOS transistor SAT.
Further, one of the input/output nodes of the data register REG is commonly connected to a pair of bit lines of an even number column and an odd number column through a write control transistor WT controlled by a write signal PROGRAM. In this case, the pair of bit lines of the even number column and the odd number column are selectively connected to the write control transistor WT by an even number column bit line selection control transistor EBT and an odd number column bit line selection control transistor OBT.
A reset transistor RT is connected to the other I/O node of the data register REG to reset the data register to a “1” state and is controlled by a reset signal RST.
Next, write, erase and read operations will be briefly explained with reference to FIG. 8.
In the write operation, write data, which is supplied from a pair of input/output lines IO, /IO through the pair of input/output gate transistors CST, is temporarily held in the data register REG. The write data is transferred to the bit line of a selected even number column or a selected odd number column through the write control transistor WT and the bit line selection control transistor EBT of the selected even number column or the bit line selection control transistor OBT of the selected odd number column. When the write data is “0”, 0V is transferred to the bit line, and when the write data is “1”, Vdd is supplied thereto.
The erase operation is executed by extracting the electrons in the floating gate to the semiconductor substrate by setting an erase voltage (for example, 21V) to the well region of the memory cell and setting 0V to the word line. Although the erase is executed on a block-by-block basis, the word lines of non-selected blocks, which are not to be erased, remain in a floating state. When the voltage of the well region is set to Vera, the potential of the floating gates potential rises by the capacitance coupling between the substrate and the word lines through the floating gates. Accordingly, in the non-selected blocks, the potential difference between the floating gates and the substrate is lowered and erase is not executed.
The read operation is executed on a page-by-page basis similarly to the write operation. At the beginning of the read operation, the data register REG is reset to the “1” state in response to the reset signal RST. Then, at the beginning of the read operation, the bit line is precharged through a precharging PMOS transistor PRT controlled by a precharge signal PRECHARGE and through an NMOS transistor RT having a gate to which a read signal READ is applied. At this time, the voltage of the read signal READ is controlled so as to set the precharge voltage of the bit line to Vdd or to set it to a potential lower than Vdd in order to increase a read speed.
Further, the activation control NMOS transistor is controlled to a “on” state by the potential at one end of the precharging PMOS transistor PRT.
Thereafter, the drain side selection gate transistor DGT and the source side selection gate transistor SGT shown in FIG. 2 are turned on while maintaining the selected word line at 0 volt to thereby determine whether or not the potential of the bit line is discharged. At this time, to allow a sufficient cell current to flow in the cell transistor connected in series to the selection cell transistor, a read voltage Vread (for example, 3.5V) is supplied to the word line corresponding to the cell transistor.
When the data of the selected cell transistor is set to “1” (when erased), since the threshold value of the transistor is lowered to a negative level, the cell current flows even if the word line is at 0V, and thus the potential of the bit line is discharged.
When the data of the selection cell transistor is set to “0” (when written), since the threshold value of the transistor is increased to 0V or more, the selected cell transistor is nonconducting, and thus the potential of the bit line remains precharged.
Thereafter, the NMOS transistor RT is turned on in response to the read signal READ, the voltage of the bit line is received by a sense amplifying NMOS transistor, a sense input NMOS transistor SA is turned on in response to a sense signal SENSE0, and the data read from the selected cell transistor is temporarily held in the data register REG. The data held in the data register REG is serially read out.
Incidentally, as bit lines are made finer, a parasitic capacitance between adjacent bit lines increases. To prevent erroneous reading caused by the increase of the parasitic capacitance, a bit line shield technology is employed as briefly explained below.
As described above, in read, whether or not a precharge potential is discharged by the cell current is determined by floating the bit line. When bit lines have a large width and adjacent bit lines are disposed at large intervals because a design rule is moderate, almost all the parasitic capacitance of a bit line is attributed to the capacitance between the bit line and the substrate, so that a read operation is not effected by the operation of the bit line.
When, however, bit lines are made thinner and intervals therebetween are made smaller by application of a more strict design rule, the parasitic capacitance of the bit lines mainly results from the capacitance therebetween. In such circumstances, a case is examined in which data “0” is written to a memory cell on a target bit line to which notice is paid and data “1” is written to two bit lines adjacent to the target bit line.
In this case, although the precharge potential of the target bit line must be maintained without being discharged, the precharge potentials of the two adjacent bit lines are discharged. Accordingly, the potential of the target bit line is also lowered by the capacitance coupling between the two adjacent bit lines, thereby the data “0” of the memory cell on the target bit line is erroneously read out as data “1”.
In the bit line shield technology used to prevent the above disadvantage, alternate bit lines are physically selected, and the potential of not selected bit lines are set to ground potential Gnd. With this arrangement, no erroneous read occurs because the potential difference of the parasitic capacitance between adjacent bit lines is fixed.
Note that in the bit line shield technology described above, a bit line of an even column and a bit line of an odd column are selected in correspondence to each other by a signal BL-even and a signal BL-odd. Further, although the number of memory cells connected to a single word line is doubled, a page size is controlled so as not to be changed by addressing when it is externally viewed.
When write/erase is executed to a flash memory, since electrons are injected into the oxide film, which is intrinsically an insulting film, of a cell transistor, the characteristics of the oxide film changes while the write/erase is repeated, thereby the write/erase characteristics of the flash memory are deteriorated.
In a NAND type flash memory, there occurs a phenomenon that an increase in the number of data rewrites (write/erase) increase a threshold value in erase. This is because an electron trap (trap level) occurs in an oxide film and electrons trapped therein prevent a tunnel current.
To obtain erase characteristics similar to initial ones regardless of an increase in the number of data rewrites, a higher erase voltage Vera or a longer erase time is necessary. Usually, there is taken a countermeasure to set an appropriate margin to an erase voltage/time so that, even if the characteristics of a memory cell is deteriorated by executing rewrite many times, the deterioration is not recognized as the deterioration of the device.
However, setting the appropriate margin to the erase voltage/time acts as excessive stress to a memory cell in an initial state, which results in that the memory cell is deteriorated rapidly. To execute erase under a most suitable condition at each timing without applying excessive stress, there is contemplated a method of adjusting the voltage or the time according to the number of data rewrites.
To realize this method, it is contemplated to store the number of data rewrites in a register and to adjust an internal voltage and the like by a controller according to the number of data rewrites. The register for storing the number of data rewrites must have a non-volatile property because it must hold information even if a power supply thereto is cut off.
In particular, since flash memories guarantee to execute rewrite 100,000 times to 1,000,000 times in a specification, a circuit is increased in size because control must be executed to count such a large number of rewrites in digital fashion and to store it in a multiplicity of storage devices (for example, 20-bits non-volatile registers) similar to, for example, memory cells.
As described above, conventional flash memories have a problem in that they must execute control to count a large number of rewrites in digital fashion and store it in many non-volatile registers, to thereby adjust a voltage, time, and the like in correspondence to deterioration of the write/erase characteristics thereof due to an increase in number of rewrites, and a circuit is increased in size.